A semiconductor memory, for example, a DRAM (dynamic random access memory), is configured with one or several memory cell arrays; wherein, within each memory cell array, several memory cells are arranged in a matrix, the memory cells on each row are connected to the same word line, and the memory cells on each column are connected to the same bit line. At the time of memory access, because a prescribed word line is selected and activated by a word line driving circuit, and a prescribed bit line is selected by a selection gate in response to an address signal input, the memory cell connected to both the selected word line and the bit line is selected, and access, such as write or read, is given to the memory cell via a sense amplifier.
FIG. 6 is a block diagram showing a configuration example of a common DRAM. As shown in the figure, the DRAM in this example is configured with 4 memory cell arrays SM0, SM1, SM2, and SM3; word line driving circuits WD01, WD02, . . . , WD31, and WD32 attached to respective memory cell arrays; and sense amplifier banks SB0, SB1, . . . , and SB4.
As shown in the figure, word line driving circuits are provided on both sides of respective memory cell arrays in the direction of the word line, and the sense amplifier banks are provided respectively on both sides thereof in the direction of the bit line.
A prescribed word line is selected and activated by the word line driving circuits provided on one side of the memory cell arrays at the time of memory access. Also, a prescribed bit line sense amplifier is selected by the selection gates in respective sense amplifier banks and connected to an input buffer.
The aforementioned word line driving circuits and the selection gate in respective sense amplifier banks are controlled respectively by a row decoder and a column decoder not shown in the figure.
In addition, neighboring memory cell arrays share the sense amplifier bank provided between them for common use. For example, the memory cell arrays SM0 and SM1 share the sense amplifier bank SB1, and the memory cell arrays SM1 and SM2 share the sense amplifier bank SB2.
As a result, the number of sense amplifiers can be reduced, and the area for the circuits can be reduced, offering an advantage as to the realization of a large capacity.
FIG. 7 is circuit diagram in which a portion of the DRAM shown in FIG. 6 is enlarged in order to show the details of the internal configuration thereof. Here, the internal configurations of the memory cell array SM1, the sense amplifier banks SB1 and SB2, and the word line driving circuits WD11 and WD12 provided around the memory cell array are shown.
As shown in the figure, the sense amplifier banks SB1 and SB2 are configured with several sense amplifiers, respectively. For example, the sense amplifier bank SB1 is configured with sense amplifiers SA0, SA2, . . . with even numbers; and the sense amplifier bank SB2 is configured with sense amplifiers SA1, SA3, . . . with odd numbers.
In the case of a semiconductor memory with such configuration, each memory cell array has almost the same configuration. Also, other sense amplifier banks SB1, SB2, and SB3 have the same configuration as the sense amplifier banks SB0 and SB4. Furthermore, the sense amplifier banks SB0 and SB4 are fundamentally identical to other sense amplifier banks in terms of their configuration except for the fact that they are connected to the memory cell array only by one side.
Here, the memory cell array SM1 and the sense amplifier banks SB1 and SB2 shown in FIG. 7 are taken as an example to explain their respective configurations and operations.
As shown in the figure, a bit line pair comprising 2 bit lines is connected to respective sense amplifiers SA0, SA1, SA2, SA3, . . . via 2 selection gates.
Among the several word lines and bit lines provided in the memory cell array SM1, only the bit lines BL0 and BL0.sub.-- connected to the sense amplifier SA0, the bit lines BL1 and BL1.sub.-- connected to the sense amplifier SA1, the bit lines BL2 and BL2.sub.-- connected to the sense amplifier SA2, the bit lines BL3 and BL3.sub.-- connected to the sense amplifier SA3, the word line WLj connected to the word line driving circuit WD11, and the word line WLj+1 connected to the word line driving circuit WD12 are shown.
The 2 bit lines connected to the sense amplifier will be referred to as a bit line and a complementary bit line, respectively, hereinafter. For example, a bit line BL0 and a complementary bit line BL0.sub.-- are connected to the sense amplifier SA0, and a bit line BL1 and a complementary bit line BL1.sub.-- are connected to the sense amplifier SA1.
As shown in the figure, memory cells are provided at the intersections of the bit line and the complementary bit line and the word lines. For example, the memory cell MC.sub.0,j is provided at the intersection of the bit line BL0 with the word line WLj, and the memory cell MC.sub.0,j+1 is provided at the intersection of the bit line BL0.sub.-- with the word line WLj+1. Similarly, the memory cell MC.sub.1,j is provided at the intersection of the bit line BL1 with the word line WLj, and the memory cell MC.sub.1,j+1 is provided at the intersection of the bit line BL1.sub.-- with the word line WLj+1.
Furthermore, in FIG. 7, positions of respective memory cells are indicated by dots, and the configuration of the memory cell is omitted. For example, the memory cell is a common DRAM memory cell configured with 1 transistor and 1 capacitor.
The sense amplifiers in the sense amplifier banks SB1 and SB2 are connected to respective bit lines and the complementary bit lines via selection gates. For example, the sense amplifier SA0 is connected to the bit line BL0 via the selection gate TG0 and further connected to the supplementary bit line BL0.sub.-- through the selection gate TG0.sub.--. Similarly, the sense amplifier SA1 is connected to the bit line BL1 via the selection gate TG1 and further connected to the supplementary bit line BL1.sub.-- through the selection gate TG1.sub.--.
For example, the selection gate is configured with an nMOS transistor, and the gates of these nMOS transistors are connected to selection signal lines T1, T2, T3, and T4, respectively.
Furthermore, the selection signal lines T1, T2, T3, and T4 are connected, for example, to the control circuit of a row decoder not shown in the figure; whereby, a prescribed signal line is selected and activated by said control circuit.
As the prescribed selection signal is selected and activated at the time of memory access, a prescribed selection gate is turned on. For example, when the selection signal line T2 is selected, said selection signal line T2 is held to a high-level, for example, to the source voltage V.sub.DD level, by the control circuit. Accordingly, the bit line BL0 and the supplementary bit line BL0.sub.-- are connected to the sense amplifier SA0, and the bit line BL2 and the supplementary bit line BL2.sub.-- are connected to the sense amplifier SA2; and, as a result, write to/read from the memory cell connected to the supplementary bit line BL0.sub.--, the bit line BL0.sub.--, the bit line BL2, and the supplementary bit line BL2.sub.-- becomes enabled.
Memory capacities of respective memory cell arrays in a semiconductor memory, such as the conventional DRAM described above, are on the increase following high-integration and enlarged capacities of semiconductor devices. Accordingly, the number of the memory cells connected to the bit lines and the complementary bit lines on one side increases, showing a tendency that resistance and capacitive load of the bit lines and the supplementary bit lines increase during read or write.
As the resistance and the capacitive load of the bit lines or the supplementary bit lines increase, a variety of problems occur at the time of memory access. For example, read speed falls during read, or accuracy of read deteriorates. Although a method is available to avoid said the problem, in which the number of the sense amplifiers is increased to reduce the load of respective sense amplifiers, this method increases the ratio of the area occupied by the sense amplifiers to that of the [entire] chip, resulting in a disadvantage in that wiring efficiency deteriorates or the chip area increases.
The extended bit line method is being suggested in order to solve the aforementioned problems. FIG. 8 is a circuit diagram showing the concept of the extended bit line method.
As shown in the figure, the bit line and the complementary bit line connected to the sense amplifier SA are split in 2 near the middle, and of the 2 split portions, those closer to the sense amplifier SA are connected to the sense amplifier SA as a bit line BL and a complementary bit line BL.sub.--, and those farther [from the sense amplifier] as an extended bit line EXBL and an extended complementary bit line EXBL.sub.--. The extended bit line EXBL and the extended complementary bit line EXBL.sub.-- [sic; EXBL] are connected to the sense amplifier (SA) via metallic wiring ML and ML.sub.--.
Furthermore, like the bit line and the complementary bit line BL.sub.--, the extended bit line EXBL and the extended complementary bit line EXBL.sub.-- are formed on a polysilicon layer, and the metallic wiring ML and ML.sub.-- are formed on a metallic layer deposited above the polysilicon layer. Furthermore, contact holes not shown in the figure are created between the metallic wiring ML and the extended bit line EXBL or between the metallic wiring ML.sub.-- and the extended complementary bit line EXBL.sub.-- for the connection of respective wiring.
However, with the extended bit line method, because the sense amplifier is connected to the bit line pair and the extended bit line pair, separate selection gates need to be provided. As shown in the figure, selection gates TC and TG.sub.-- are laid between the sense amplifier SA and the bit line BL as well as the complementary bit line BL.sub.--, respectively; and selection gates TGE and TGE.sub.-- are laid between the sense amplifier SA and the bit line EXBL as well as the complementary bit line EXBL.sub.--, respectively.
The gates of the selection gates TG and TG.sub.-- are connected to a selection signal line SHRS, and the gates of the selection gates TGE and TGE.sub.-- are connected to a selection signal line SHRE.
Access can be made to the memory cell connected to the bit line BL and the complementary bit line BL.sub.-- by selecting and activating the selection signal line SHRS, and access can be made to the memory cell connected to the bit line EXBL and the complementary bit line EXBL.sub.-- by selecting and activating the selection signal line SHRE.
With the aforementioned extended bit line method, resistance and capacitive load of the bit line connected to the sense amplifier can be reduced, fall in the access speed and deterioration of reading accuracy can be prevented, and a large memory capacity can be realized. However, as shown in the figure, separate selection gates are needed for the bit line pairs and the extended bit line pairs connected to respective sense amplifiers, and 4 control signal lines are needed for each sense amplifier to control the selection gates when the bit line and the extended bit line are provided symmetrically on both sides of the sense amplifier. In the case of the conventional DRAM shown in FIG. 7, only 2 selection signal lines are needed for each sense amplifier to control the selection gates. Therefore, the control circuit of the conventional semiconductor memory cannot be used, so a new control circuit is needed.
The present invention was made in the light of this situation, and its purpose is to present a semiconductor memory with which the memory capacity can be increased while reducing the resistance and the capacitive load of the bit line through the realization of a control circuit capable of generating a selection signal for the selection of a bit line and an extended bit line using the extended bit line method.